07-Processor

`include "core_struct.vh"
module RegFile (
  input clk,
  input rst,
  input we,
  input CorePack::reg_ind_t  read_addr_1,
  input CorePack::reg_ind_t  read_addr_2,
  input CorePack::reg_ind_t  write_addr,
  input  CorePack::data_t write_data,
  output CorePack::data_t read_data_1,
  output CorePack::data_t read_data_2
);
  import CorePack::*;
  integer i;
  data_t register [1:31]; // x1 - x31, x0 keeps zero
  // fill your code
endmodule

// fill your code
assign read_data_1 = (read_addr_1 == 5'd0) ? 64'd0 : register[read_addr_1];
assign read_data_2 = (read_addr_2 == 5'd0) ? 64'd0 : register[read_addr_2];
always_ff @(posedge clk or posedge rst) begin
  if (rst) begin
    for (i = 1; i < 32; i++) begin
      register[i] <= 64'd0;
    end
  end else if (we && write_addr != 5'd0) begin
    register[write_addr] <= write_data;
  end
end

// fill your code
always_comb begin
  case (cmp_op)
    // CMP_NO:   res = 0; // 表示不是比较类型
    CMP_EQ:   res = (a == b) ? 1 : 0;
    CMP_NE:   res = (a != b) ? 1 : 0;
    CMP_LT:   res = ($signed(a) < $signed(b)) ? 1 : 0;
    CMP_GE:   res = ($signed(a) >= $signed(b)) ? 1 : 0;
    CMP_LTU:  res = (a < b) ? 1 : 0;
    CMP_GEU:  res = (a >= b) ? 1 : 0;
    // CMP7:     res = 0;
    default:  res = 0;
  endcase
end